A transmission gate is a circuit element that is inserted serially in a transmission path for controlling transmission therepast. Essentially it is a circuit that includes a switch serially coupled in the transmission path that can be either open, i.e., a high impedance, or closed, i.e., a low impedance or short.
Transmission gates typically employ a metal-oxide-semiconductor (MOS) transistor as the switch. In such an application the source-drain path of the MOS transistor is in the transmission path and a control signal applied to the gate electrode serves to switch this path between a high (when the transistor is turned off) and a low (when the transistor is turned on) impedance state.
However, it is a characteristic of a MOS transistor that it has a first parasitic capacitor between the gate and source and a second parasitic capacitor between the and gate and drain that serve to shunt signal charge both when the transistor is being turned on and again when it is being turned off. Such capacitive shunting serves to slow the onset of the high impedance state when the transistor is turned off and the onset of the low impedance state when the transistor is turned on. Additionally, charge injected by a control pulse applied to the gate of the transistor can be trapped at the output terminal (which is typically coupled to a high impedance load). At high switching speeds, this trapped charge can reduce the rate of transition to the high impedance state of the switch. To minimize this charge pumping, the usual practice hitherto has been to associate the transistor with a pair of dummy transistors used as two terminal capacitors through which a partially compensating inverse charge is injected (see FIG. 1). Still further, the charge injected can change the voltage levels of signals being transmitted through the transmission gate and can thus degrade the accuracy of these signals. These problems are particularly of interest in some analog-to-digital converters which require high accuracy input signals.
Referring now to FIG. 1, there is shown a transmission gate 10 which includes n-channel MOS transistors 12, 14 and 16 and first and second inverters 18 and 20. Inverter 18 is used as a buffer and is optional. Transmission gate 10 controls a transmission path from a terminal 22, which is coupled to the drain and source of transistor 14 and to the drain of transistor 12, to a terminal 24 which is coupled to the drain and source of transistor 16 and to the source of transistor 12.
An output terminal of an n-channel transistor is generally denoted as the drain if positive current flows into same and passes through the channel of the transistor and exits at the other output terminal which is denoted as the source. If the direction of current flow through the transistor reverses, the drain and source designations of the output terminals reverse.
An output terminal of a p-channel transistor is generally denoted as the source if positive current flows into same and passes through the channel of the transistor and exits at the other output terminal which is denoted as the drain. If the direction of current flow through the transistor reverses, the drain and source designations of the output terminals reverse.
A control signal input terminal 26 is coupled to an input of inverter 20. An output of inverter 18 is coupled to an input of inverter 20, to the gate of transistor 12 and to a terminal 28. An output of inverter 20 is coupled to the gates of transistors 14 and 16 and to a terminal 30. A first conductor 32 shorts the drain and source of transistor 14 together and a second conductor 34 shorts the drain and source of transistor 16 together. Transistors 14 and 16, with their drains and sources shorted together, act as capacitors and as such may be denoted as capacitors 14 and 16 with the gate of each serving as a first capacitor terminal and the source and drain of each serving as a second capacitor terminal. Capacitors Cgs and Cgd, shown in dashed lines, are the parasitic gate to source capacitance and gate to drain capacitance of transistor 12. Cgs and Cgd are typically equal because of the symmetrical structure of the typical MOS transistor.
The dimensions of transistors 14 and 16 are typically selected to be identical to those of transistor 12 except that the channel width of each is typically one-half of that of the channel width of transistor 12. This to a large order makes the capacitance of each of transistors 14 and 16 equal to Cgs and Cgd, respectively.
During operation a control voltage pulse (not shown in FIG. 1) is applied to terminal 26 and same is inverted by inverter 18 and then by inverter 20. This voltage pulse serves to turn on and turn off transistor 12. In doing so charge is injected via Cgs and Cgd to terminals 22 and 24, respectively. This injected charge can change the potential of terminals 22 and 24 which can in some applications modify and/or degrade information being transmitted through transmission gate 10. The trapped charge is a function of the rate of transition of the transistor to the high impedance state of transmission gate 10.
In operation, the capacitors 14 and 16 are designed to provide approximate charge compensation to the transistor 12 for capacitive coupled current flowing therein by supplying or withdrawing and appropriate equal amount of capacitive coupled charge to terminals 22 and 24, respectively.
However, for good compensation, it is necessary that the control voltage pulse applied to the gate (terminal 28) of the transistor 12 be exactly equal in amplitude and opposite in phase to the control voltage pulse applied to the gates (terminal 30) of capacitors 14 and 16. In practice it is difficult to achieve perfect compensation due to several effects but primarily because it is difficult to get the phases exactly opposite. In particular, any time delay introduced in the control voltage pulse by inverter 20 causes an error in achieving exactly a 180 degree phase difference. Failure to get perfect compensation can result in undesirable charge buildup in the transistor 12 when it is turned off. It can also change the potential of terminals 22 and 24 when transistor 12 is turned on but this injected charge is usually dissipated to a low output impedance signal source (not shown) coupled to terminal 22.
Referring now to FIG. 2, there are graphically shown voltage waveforms A (solid line) and B (dashed line) appearing at the gate (terminal 28) and the gates (terminal 30) of transistors 14 and 16, respectively, with the x-axis being time T (nano-seconds) and the y-axis being voltage V (volts). Waveform A leads waveform B because of a delay introduced by inverter 20.
Referring now to FIG. 3, there is graphically shown a current varying waveform appearing on terminal 24 with the x-axis being time T (nano-seconds) and the y-axis being charge Q (coulombs). The time scales of FIG.'s 2 and 3 are essentially identical.
For the case depicted, the transistor 12 is turned on before the transistors 14 and 16 are turned off. As a result, extra charge is injected at the source/gate and drain/gate capacitances and it is trapped in the source capacitance of the transistor 12 once transistor 12 is off. This results in the positive offset voltage between T=t3 and T=t4 of FIG. 3.
In the opposite case (not depicted) where the control pulse to the gates of transistor 14 and 16 leads, charge injected from these transistors "bleeds" back to a signal source (not shown) since the transmission gate 10 is still on (transistor 12 is turned on). The result is that excess charge is injected by Cgs and Cgd into terminals 22 and 24 where it is trapped since the conductance of the transmission gate lo goes to zero before the signal applied to the gate of transistor 12 (terminal 28) reaches its off level, a "0".
Another problem with circuitry lo is that it is difficult to dynamically match the capacitance of the n-channel transistors used as capacitors with the Cgd and Cgs parasitic capacitances when an MOS transistor is enabled (biased on) it's Cgd and Cgs are greater than when it is disabled (biased off). Circuitry 10 uses opposite logical level signals to control the n-channel transistors. This means that during portions of the operation that one n-channel transistor is enabled and the other two are disabled and during other portions of the operation the reverse is true. It is thus difficult to match capacitances as closely as may be desired in some applications.
It is desirable to have an MOS transistor transmission gate which has better compensation for injected charge than the transmission gate 10 of FIG. 1.